ALL THE BEST!!!
VLSI V5 EFC-DELHI-19THAUGUST2024
1 / 50
How will the number -8`d4 ( in Verilog) be internally represented as bits?
2 / 50
Computer-assisted graphical entry is done through
3 / 50
Which of the following representation of a design has the highest degree of abstraction
4 / 50
Which can bring about variations in threshold voltage?
5 / 50
An event-based RTL simulator keeps the events ordered in the event queue according to
6 / 50
Which among the following is a variable cost in standard cell based design
7 / 50
In basic inverter circuit _____________ is connected to ground.
8 / 50
As the channel length is scaled down, influence of mobility
9 / 50
Which of the following data types can store value during Verilog simulation
10 / 50
Which of the following statement is incorrect about a Verilog function?
11 / 50
For which of the following figures of merit, dedicated hardware can be better than the same function implemented as software running on a general purpose processor.
12 / 50
What is the purpose of carrying out hardware software partitioning for a system?
13 / 50
In CMOS logic circuit, the switching operation occurs because:
14 / 50
Submicron CMOS technology is
15 / 50
The oxide layer below the first metal layer is deposited using__________
16 / 50
______________ Impurities are added to the wafer of the crystal.
17 / 50
Conducting layer is separated from substrate using
18 / 50
Increasing fan-out ____________ the propagation delay.
19 / 50
Mobility depends on ________
20 / 50
Pass transistors are transistors used as ________
21 / 50
What are the advantages of BiCMOS?
22 / 50
Finite state machines are used for
23 / 50
Which of the following statements/are true with respect to testing?
24 / 50
A bit can be stored when
25 / 50
Rise time and fall time can be equalized by
26 / 50
Ids depends on ___________
27 / 50
The size of a transistor is usually defined in terms of its
28 / 50
The nature of physical layout verification software depends on
29 / 50
How many transistors are required to implement a X-input dynamic CMOS logic?
30 / 50
In nMOS inverter configuration depletion mode device is called as ________
31 / 50
Approach used for design process are
32 / 50
33 / 50
_______ layer should be over ______ layer.
34 / 50
Simulators are available for
35 / 50
How many transistors might bring up latch up effect in p-well structure?
36 / 50
In inverter during logic 1 to 0 transition, capacitance discharges at
37 / 50
The area of CMOS inverter is proportional to
38 / 50
Which of the following statements is incorrect about code coverage
39 / 50
Size of the die is determined using
40 / 50
Stick diagrams are those which convey layer information through?
41 / 50
In latch-up condition, parasitic component gives rise to__________ conducting path.
42 / 50
NMOS transistors are used as pass transistor, and a gate voltage (V GS ) much larger than the threshold voltage(V THN ) is applied. On the source side of this NMOS pass transistor, a voltage V DD is applied. What will be the drain voltage of this NMOS transistor.? Please assume that the body of the transistor is grounded.
43 / 50
Contact cuts should be ____ apart.
44 / 50
Electromigration is a
45 / 50
Consider the first level metal interconnect that has cross sectional dimensions of w= 0.35 μm and t=0.7 μm and runs over an oxide layer that has a thickness of Tox=0.9 μm. The capacitance per unit length is________
46 / 50
The magnetic core memories have been replaced by semiconductor RAMs, why?
47 / 50
When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:
48 / 50
What are the advantages of design rules?
49 / 50
Which of the following statements about non-blocking assignments in Verilog is incorrect?
50 / 50
In MOS transistors _______________ is used for their gate.
