VLSI-LBI-JODHPUR NOV BATCH DATED 13th JAN 2025 - MSME

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VLSI- LBI JODHPUR NOV BATCH1-13TH JAN 2025

1 / 50

How will the number -8`d4 ( in Verilog) be internally represented as bits?

1111 1111

1111 1110

1111 1100

1111 0000

2 / 50

Bonding pads are placed

in the chip

exactly at the centre of chip

edge of the chip

above the chip

3 / 50

Larger energy bandgap _____ parasitic capacitances.

increases

decreases

maintains constant

does not affect

4 / 50

What is the output of the following two equations in Verilog?
i) assign Y=4’b1010 & 4’b0110;
ii) assign Y =4’b1010&& 4’b0110;

i) 4’b0010 ii) 4’b0001

i) 4’b0101 ii) 4’b1001

i) 4’b0110 ii) 4’b0010

i) 4’b0010 ii) 4’b0010

5 / 50

Which of the following statements is incorrect

Multiple dies are fabricated on a single silicon wafer

Silicon wafers are sliced out from silicon ingots

We get silicon ingots from a silicon die

We obtain a chip after packaging a die

6 / 50

Which of the following statements is incorrect

The semiconductor manufacturing plant where integrated circuis are fabricated is called a semiconductor foundry

Fabless design companies design integrated circuits

Setting up a semiconductor foundry requires a huge investment

Designing integrated circuits is done in semiconductor foundries

7 / 50

Which of the following tasks is typically NOT performed by a testbench in simulation based RTL verified

Interact with the simulator

Applies stimulus

Observes the response

Perform logic synthesis

8 / 50

Which of the following statements best describes the purpose of behavior systems in VLSI design flow?

It converts an algorithm to an equivalent design in RTL

It converts an algorithm to a binary execution

It convert an algorithm into sequential of zeros and ones

It convert an algorithm to an assembly language code

9 / 50

Which of the following statements about non-blocking assignments in Verilog is incorrect?

The execution of the next statement is done after the current non-blocking assignment is fully executed

The symbol for non-blocking assignment is <=

The execution of the next statement is not blocked until the current non-blocking assignment is executed

The RHS of a non blocking assignment can be a Verilog expression

10 / 50

Which among the following is a variable cost in standard cell based design

Design cost

Cost of mask

Cost of design tools

Cost of die

11 / 50

How many transistors are required to implement a X-input dynamic CMOS logic?

X+1

X+2

X+3

12 / 50

The variable A contains the bit sequence (1011) the variable Y is obtained by applying the reduction operator, Y=|A what will be the final value of Y?

13 / 50

Which of the following statements/are true with respect to testing?

It is used to guarantee that a given manufactured circuits is free from all defects

It is used to increase the confidence in the correct working of a manufacturing circuit

It is used to verify that the design is correct

all of the above

14 / 50

What is the purpose of carrying out hardware software partitioning for a system?

It gets rid of the software in the system

It chooses an optimal combination of hardware and software to implement the system

It gets rid of all the hardware in the system

It compiles the software of the system

15 / 50

In latch-up condition, parasitic component gives rise to__________ conducting path.

low resistance

high resistance

low capacitance

high capacitance

16 / 50

Inverter threshold voltage is the point where

Vin = Vt

Vout = Vt

Vin = Vout

Vout lesser than Vin

17 / 50

Which of the following data types can store value during Verilog simulation

Wire

Wand

Wor

Reg

18 / 50

Which of the following statements is incorrect about code coverage

Help identify sections of DUV’s source code that didn’t execute during verification

Help perform timing analysis of the design

Helps monitor the progress of the verification effort

Helps assess the quality of verification

19 / 50

What is the purpose of masks in photolithography

Define shapes/ patterns that need to be obtained on the wafer

Isolate multiple layers of interconnect

Etch silicon during chemical etching

Oxidize silicon after photolithography

20 / 50

Find the voltage Vx (assume vtn is 0.3v)

0.7V

0.4V

21 / 50

In the adder, sum is stored in

series

cascade

parallel

registers

22 / 50

Input and output pads are made up of

polysilicon

metal

silicon

carbon

23 / 50

Which of the following statements best describes Moore’s prediction or Moore’s law

Every concept has an equal and opposite reaction

The number of components in an IC can never be increased

The number of components in an Ic realized at minimum cost will double every year or every two years

The sizes of transistors in Ics realuzed minimum cost will remain constant

24 / 50

NMOS transistors are used as pass transistor, and a gate voltage (V GS ) much larger than the threshold voltage(V THN ) is applied. On the source side of this NMOS pass transistor, a voltage V DD is applied. What will be the drain voltage of this NMOS transistor.? Please assume that the body of the transistor is grounded.

V DD - V THN

V DD -0.5V DD

V DD -0.5V GS

V DD

25 / 50

For which of the following figures of merit, dedicated hardware can be better than the same function implemented as software running on a general purpose processor.

Risk due to bug

Development time

Speed

Flexibility in implementation and customization

26 / 50

The Higher Noise Margin is given by:

VOH – VIH

VIH – VOH

VIH ~ VOH(Difference between VIH and VOH, depends on which one is greater)

All of the mentioned

27 / 50

Which design is preferred in n-bit adder?

many pass transistors in series

many pass transistors with suitable buffer

many pass transistors without suitable buffer

many pass transistors in parallel

28 / 50

A digital multiplexer is a combinational circuit that selects___________

One digital information from several sources and transmits the selected one

Many digital information and convert them into one

Many decimal inputs and transmits the selected information

Many decimal outputs and accepts the selected information

29 / 50

Pass transistors are transistors used as ________

switches connected in series

switches connected in parallel

inverters used in series

inverter used in parallel

30 / 50

Mobility degradation observed in short channel MOS device due to

decrease in channel length

threshold voltage decreases

Increases in oxide thickness

velocity saturation

31 / 50

Increasing fan-out ____________ the propagation delay.

increases

decreases

does not affect

exponentially decreases

32 / 50

_______ layer should be over ______ layer.

ntype, polysilicon

polysilicon, ntype

ptype, ntype

ntype, ptype

33 / 50

The relation between threshold voltage and Noise Margin is:

Vth = sqrt(Noise Margin)

Vth = NMH – NML

Vth = (NMH+NML)/2

None of the metioned

34 / 50

Which of the following statement is incorrect about a Verilog function?

A function can have one or more inputs

A function will have one output

A function can call another function

A function can call another task

35 / 50

An event-based RTL simulator keeps the events ordered in the event queue according to

Speed of the processor on which simulation is run

Randomly

Simulation time of the event

Delay of circuit elements in the synthesized netlist

36 / 50

Logic reduces the transistor counts which are used to make different logic gates by eliminating the redundant transistor is called ____________

Resistive transistor logic

Transistor transistor logic

Pass transistor logic

None of the above

37 / 50

In the pulldown network of a NAND logic shown below, to obtain a high speed of operation , the critical signal must be connected to the gate of ____________

38 / 50

Stick diagrams are those which convey layer information through?

thickness

color

shapes

layers

39 / 50

Which among the following design styles require maximum design effort

standard cell-based design

Full custom design

Gate array-based-design

FPGS based design

40 / 50

A____________ is a level sensitive device while a ______depends on clock pulse for their operation.

Latch ; register

Inverter; latch

D-flipflop; latch

41 / 50

Which of the following statement will be execute from
the below program?

reg [3:0] x=4’b000x;
always @(*)
begin
casex(x)
4’b0000 : statement 1;
4’b0100 : statement 2;
4’b1100 : statement 3;
4’b0001 : statement 4;
endcase
end

Statement 2

Statement3

Statement1

Statement4

42 / 50

For a sequential circuit, which of the following is true

T > t c-q + t logic + t su

T < t c-q + t logic + t su

T > t c-q + t logic + t su + t hold

T t c-q + t logic + t su + t hold

43 / 50

In nMOS inverter configuration depletion mode device is called as ________

pull up

pull down

all of the mentioned

none of the mentioned

44 / 50

The oxide layer below the first metal layer is deposited using__________

diffusion method

chemical vapour deposition

solid deposition

scattering method

45 / 50

Noise Margin is:

Amount of noise the logic circuit can withstand

Difference between VOH and VIH

Difference between VIL and VOL

All of the Mentioned

46 / 50

In basic inverter circuit _____________ is connected to ground.

source

gates

drain

resistance

47 / 50

How many transistors might bring up latch up effect in p-well structure?

two

three

one

four

48 / 50

Buffers are needed to drive

small capacitance

large capacitance

small resistance

large resistance

49 / 50

Which of the following representation of a design has the highest degree of abstraction

As RTL in Verilog

As an algorithm in the programming language C

As connection of logic gates in Verilog

As the layout of transistors and interconnects

50 / 50

Mobility depends on ________

Transverse electric field

Vdd

Channel length

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